This application claims the benefit of Korean Patent Application No. 10-2006-0137360, filed on Dec. 29, 2006, which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention relates to a semiconductor device and a method of fabricating a semiconductor device with gap-filling and an interlayer dielectric layer between word lines.
2. Discussion of the Related Art
As the high integration of a semiconductor device is progressed, the spaces between patterns have become narrower, meaning that the process of filling an interlayer dielectric layer for the interlayer insulation between metal-wirings in the spaces has become increasingly difficult.
In particular, the cell arrays of semiconductor devices are formed with a minimum line width and pitch, meaning that the gap between the word lines is often too narrow to facilitate a sufficient filling of the gap formed at the both sides of the word line.
In flash memory devices, the vertical size of the word line is large enough that the gap between the word lines has a high aspect ratio compared to other devices. Further, since the width of the lower portion word line is larger than the upper portion of the word line, the gap between the word lines at the area close to the substrate is small, meaning that the interlayer dielectric layer may not completely fill the gap, creating a void in the gap.
FIG. 1 is a cross-sectional view of a semiconductor device of the current art. FIG. 1 describes a flash memory device as an example of a semiconductor device. The flash memory device includes a device isolating layer 12 formed on the semiconductor substrate 10 which defines active areas 18 and a plurality of word lines 14 arranged across the top of the active areas 18 of the device isolating layer 12. The gaps between adjacent word lines 14 alternate between relatively narrow gaps 26 and wide gaps 28. The area in the relatively narrow gap 26 forms a source area 22, while the portion in the relatively wide gap 28 forms a drain area 24 which may be connected to a bit line contact (not shown).
In order to connect the source areas 22 in a direction parallel with the word lines 14, a portion of the device isolating layer 12 between the word lines 14 below each narrow gap 26 is removed, and the sides of the word lines 14 are formed with spacer dielectric layers 16s and 16d. The spacer dielectric layer 16s is formed between alternating adjacent word lines 14 in order to fill the narrow gap 26, and the spacer dielectric layer 16d is formed between in the remaining word lines 14 in order to reduce the size of the wide gap 28.
Typically, an interlayer dielectric layer 20 is subsequently formed over the substrate 10, word lines 14, and the spacer dielectric layers 16s and 16d, so as to completely fill the gaps 26 and 28 between the word lines. Unfortunately, however, because of the small size and the shape of the resulting gap 20a between the word lines 14, which often has a wider base than top, it is often difficult to sufficiently fill the resulting gap 20a with the interlayer dielectric layer 20, leaving voids or bubbles in the resulting gap 20a near the substrate 10.